1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to the structure of a contact hole which extends between wire layers in a multi-layer wiring structure of a semiconductor device, and a method of fabricating the contact hole structure.
2. Description of the Related Art
The trend of higher miniaturization and integration in semiconductor devices is still in vigorous advancement, and at present, super-high integrated semiconductor devices have been developed and made on an experimental basis, such as logic devices designed on the dimensional basis of approximately 0.15 μm, memory devices such as 1-gigabit dynamic random access memory (GbDRAM), and the like. However, such higher miniaturization in semiconductor devices makes it quite difficult to form contact holes which are essential in any structure of semiconductor devices.
Generally, a semiconductor device is manufactured by sequentially laminating patterns formed of a variety of materials such as a metal film, a semiconductor film, an insulating film and the like on a semiconductor substrate to complete the semiconductor device. The lamination of patterns for a semiconductor device involves a photolithographic process in which a mask is placed in registration with an underlying pattern, which has been formed in the previous process, and a next overlying pattern is aligned to and formed on the underlying pattern.
The alignment is similarly required in the formation of miniature contact holes. For example, in a structure comprised of a diffusion layer formed on the surface of a silicon substrate, and a pair of overlying wire patterns each of which constitutes a gate electrode of a MOS transistor, a contact hole must be formed through an interlayer insulating film such that the contact hole is positioned among the wire patterns of the gate electrodes and reaches a predetermined region in the diffusion layer.
In the formation of contact holes as mentioned above, the increasingly miniaturized dimensional basis makes the mask matching and alignment gradually more difficult. To solve this problem, a self-aligned contact (SAC) has been proposed since it can eliminate a design margin for alignment on a photomask. The SAC technology is now deemed indispensable for forming miniature contact holes, and such SAC technology has been used in practice.
When the SAC technology is relied on to form a contact hole, a silicon nitride (SiN) film is typically used as an etching stopper for an interlayer insulating film. A variety of techniques have been proposed for the formation of contact holes by the SAC technology, as represented by Laid-open Japanese Patent Application No. 9-050986 (JP, 09050986, A). In the following, a method of forming a contact hole described in JP, 09050986, A will be described with reference to FIGS. 1A to 1C.
First, as illustrated in FIG. 1A, gate insulating film 102 is formed on the surface of silicon substrate 101, and gate electrode 103 is formed on gate insulating film 102. Here, gate electrode 103 is designed in a so-called tungsten polyside structure as comprised of a tungsten silicide (WSi) layer and a polycrystalline silicon layer. Then, offset oxide film 104 is formed on gate electrode 103. Further, side wall insulating film 105 is formed on side walls of gate electrode 103 and offset oxide film 104. Here, offset oxide film 104 and side wall insulating film 105 are made of SiOx films, where the SiOx film is a silicon-based oxide film.
Source/drain diffusion layer 106 is formed in a LDD (lightly doped drain) structure, followed by lamination of SiN etching stopper film 107 and interlayer insulating film 108. Here, SiN etching stopper film 107 is a silicon nitride film of approximately 50 nm thick deposited by a low pressure (LP) CVD (chemical vapor deposition) method. On the other hand, interlayer insulating film 108 is an SiOx film.
Next, resist mask 109 is formed by photolithography, and interlayer insulating film 108 is selectively etched to form a contact hole 110, as illustrated in FIG. 1B. Here, SiN etching stopper film 107 functions as an etching stopper which completely protects offset oxide film 104 and side wall insulating film 105 from dry etching.
Next, changing an etching gas for use in the dry etching, SiN etching stopper film 107 is selectively etched away. In this manner, wire 111 is formed as illustrated in FIG. 1C. Specifically, wire 111 is connected to source/drain diffusion layer 106 through contact hole 110a formed through interlayer insulating film 108 and SiN etching stopper film 107. Here, wire 111 is a well known laminate wire layer.
As semiconductor devices are further miniaturized, the SAC technology is more frequently utilized, with the miniaturization in the SAC structure essentially accompanied thereto. Particularly, the SAC structure must be miniaturized more and more for forming a contact hole, by the SAC technology, for connecting a diffusion layer with a bit line in a memory cell comprised of one capacitor and one MOS transistor, as is the case with a memory device.
Next, the miniaturization of the SAC structure will be described with reference to FIGS. 2A to 2C.
As illustrated in FIG. 2A, gate insulating films 202, 202a are formed on the surface of silicon substrate 201, and gate electrodes 203, 203a are formed respectively on gate insulating films 202, 202a. Here, gate electrodes 203, 203a are in a so-called tungsten polyside structure as comprised of a WSi layer and a polycrystalline silicon layer. Then, protective insulating layers 204, 204a are formed on gate electrodes 203, 203a, respectively. Here, protective insulating layers 204, 204a are silicon nitride films. Then, source/drain diffusion layers 205, 205a are formed.
Next, as illustrated in FIG. 2B, blanket insulating film 206 is deposited over the entire surface. This blanket insulating film 206 is a silicon nitride film of approximately 30 nm thick, and is applied on the surfaces of gate electrodes 203, 203a, protective insulating layers 204, 204a, and source/drain diffusion layers 205, 205a. The structure in FIG. 2B largely differs from the example illustrated in FIGS. 1A to 1C in that no side wall insulating films are formed on side walls of the gate electrodes.
Next, as illustrated in FIG. 2C, interlayer insulating film 207 is laminated on blanket insulating film 206. Here, interlayer insulating film 207 is a silicon oxide film which has its surface planarized by a chemical mechanical polishing (CMP) method.
Next, a photoresist mask, not shown, is provided and used as an etching mask for dry-etching interlayer insulating film 207. In addition, a portion of underlying blanket insulating film 206 is selectively etched to form contact hole 208 which extends to the surface of source/drain diffusion layer 205.
Although not shown, subsequently, a wiring plug is formed in contact hole 208, and a bit line is disposed thereon for connection with the wiring plug. Thus, the SAC-based wiring structure is completed.
The inventor has investigated contact holes formed in a self-aligned manner with parallelly routed wire patterns, i.e., the SAC structure, as described above, from a variety of aspects including the miniaturization therefor. As a result, the inventor found that the method of forming the SAC structure in a miniaturized semiconductor device, as illustrated in FIGS. 2A to 2C, would deteriorate the insulating property in the contact hole. The reason will be discussed below with reference again to FIGS. 2A to 2C.
As illustrated in FIG. 2C, after forming contact hole 208 through the interlayer insulating film by dry etching, corner portions of protective insulating layers 204, 204a are sputter-etched on gate electrodes 203, 203a. Blanket insulating film 206 applied in contact hole 208 is also sputter-etched. Thus, corroded portions 209, 209a are formed in contact hole 208, as illustrated in FIG. 2C.
Generally, for dry-etching interlayer insulating film 207 made of a silicon oxide film, a reactive gas is excited by a plasma for use in the dry etching so as to reduce an etching rate for protective insulating layers 204, 204a and blanket insulating film 206 made of silicon nitride films. In other words, the etching gas is selected to provide a large ratio of the etching rate for silicon oxide film to the etching rate for silicon nitride film.
Here, the inventor found as a result of a variety of attempted experiments, that in the formation of the very small or miniature SAC structure as described above, ions within the plasma excited gas promoted the sputtering in the corner portions of protective insulating layers 204, 204a. Such a sputtering effect becomes more prominent as the aspect ratio, that is, ratio of the depth to the opening diameter, of contact hole 208 is higher. This sputtering effect causes a lower apparent ratio of the etching rate for silicon oxide film to the etching rate for silicon nitride film, resulting in corroded portions 209, 209a as mentioned above.
Such corroded portions 209, 209a, if any, cause short-circuiting between gate electrodes 203, 203a and the aforementioned bit line. Otherwise, the insulating property is degraded between these components. As a result, this causes a reduced manufacturing yield rate in mass production of semiconductor devices.
However, an attempt to reduce the corroded portions as mentioned above would require the SAC structure having side wall insulating films as described in connection with FIGS. 1A to 1C, thereby making the miniaturization difficult in the structure between gate wires. Eventually, difficulties in the miniaturization of the structure constitute a large bottle neck for higher integration and higher density for semiconductor devices such as memory devices.